Compact pipelined matrix multiplier utilizing encoding and shifting

Abstract

A circuit and algorithm for multiplying three matrices includes plurality of processor element (PE) column. Each PE column includes a plurality of processor element (PE) units and each unit includes a data register for receiving and storing a plurality sets of numbers of a row of a first matrix and a corresponding column of a second matrix. Each of the PE units is connected to another PE units of the PE column sequentially transmitting the sets of numbers between the registers in a time progressive manner. Each of the PE units further includes a multiplication processing unit for receiving a plurality of bits of the sets of numbers from the �storage means! register, the multiplication processing unit processes the plurality of bits to generate a partial processing result At least one of the PE units using the partial processing result generates a multiplication of the sets of numbers whereby each of the PE column performs a matrix multiplication of a column of the second matrix. Since the number of PE columns is equal to the number of columns of the second matrix, the multiplication circuit thus performs a multiplication of the first matrix to the second matrix.