The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 1999

Filed:

Nov. 20, 1997
Applicant:
Inventors:

Robert S Wrathall, Scotts Valley, CA (US);

Kevin P D'Angelo, Santa Clara, CA (US);

Assignee:

Impala Linear Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
323316 ; 323315 ;
Abstract

A current sense circuit utilizes multiple resistive reference switches connected in electrical series to reduce the level of required reference current (Iref), while maintaining the integrity of tracking current (Iout) through a resistive power switch. Typically, all of the reference switches are MOS transistors connected in electrical series. The first embodiment includes establishing a ratio (n) of series reference transistors to series pilot transistors, n>1. In another embodiment, the series connection of reference switches is in parallel with a single reference resistor and is identical to a series connection of a number (NP) of pilot switches. In a third embodiment, the techniques of the first two embodiments are combined (i.e., n>1 and NP>1). The current sense circuit is utilized to monitor output current through a power switch from a circuit load. Each of the pilot and reference switches is fabricated such that conductivity through the power switch would be greater than conductivity through an isolated pilot or reference switch by a scaling factor. In the preferred embodiment, a scaling factor (SF) is established by fabricating the pilot and reference switches to have gate widths that are smaller than the gate width of the power switch, such that Iref=Iout/(SF.times.n.times.NP).


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