The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1999
Filed:
Jun. 13, 1996
Kenneth M Hays, Anaheim, CA (US);
Boeing North American, Inc., Seal Beach, CA (US);
Abstract
A process is provided for protecting, containing, and/or completing fragile microelectronic and microelectromechanical (MEM) structures on a low conductivity substrate during anodic wafer bonding of a covering wafer. The wafer includes raised areas that contact the substrate at selected bonding regions to support the wafer as a covering structure over the substrate. The covering wafer includes additional raised areas, such as pillars or posts, that contact selected electric circuit lines on the substrate to form temporary shorts through the wafer. During anodic bonding of the wafer to the substrate, the temporary shorts maintain the connected circuit lines and microstructures at nearly the same electric potential to prevent unwanted arcing and electrostatic forces that could damage the fragile structures. The pillars or posts can be formed at the same time as the raised bonding areas, but on unwanted and otherwise unused portions of the covering wafer. Anodic bonding produces only weak bonds between the wafer posts and the metallic conductor material of the circuit lines. After anodic bonding, the unwanted portions of the covering wafer can be removed to leave covering structures over the selected microstructures. Because of the weak bonds, removal of the unwanted portions of the wafer also removes the posts and eliminates the temporary shorts, with no additional processing needed to electrically separate the circuit lines on the substrate.