The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 1999
Filed:
Mar. 13, 1997
Sudhaker Reddy Anumula, Starkville, MS (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
The present invention significantly lowers the continuous write cycle ICC, thus lowering the overall ICC specification, for multi-port (and single port) memory devices without significant changes in ICC.sub.WR and ICC.sub.RR currents. In one embodiment, a circuit for the generation of a Write Data select signal (i.e., TTL.sub.-- SEL) according to the present invention employs a unique 'write power-down' delay (t.sub.WPD) which is a function of 'CE+WE' (chip select and write enable) and incorporates the delay into the generation of the Write Data select signal, TTL.sub.-- SEL. The delay t.sub.WPD is provided by a delay device and is preferential. That is, a delay is provided when the internal write data select signal, i.e., TTL.sub.-- sel (which is a function of 'CE+WE'), transitions from logic '1' to a logic '0', but no delay is produced when TTL.sub.-- sel transitions from a logic '0' to a logic '1'.