Merged buffer signal switch

Abstract

A signal switch with merged buffer architecture has multiple input ports connected to a circuit switch matrix which partially sorts the input signals based on output port destination. The circuit switch matrix is connected to multiple merged buffers, each in turn connected to a corresponding output port and feedback. Input signals entering the circuit switch matrix are normally sent to the buffer attached to the destination output port of the input signal, but, if more than one input signal is contending for an output port, all but the first contending input signal are misrouted to merged buffers that are not busy. The location in memory of all of the correctly routed and misrouted input signals in the switch is tracked by a control, which also routes input signals to their output port destinations from the merged buffers, and reroutes misrouted input signals to the correct buffers. The control does not reroute a misrouted signal until its intended buffer is no longer busy, so that each input signal is rerouted at most once. The control can also track the priority, sequence number, and output port destination of each input signal, in order to give preference to the higher priority input signals going to a particular output port. Buffer overflow can be minimized and switch resources more efficiently utilized by denying rerouted input signals access to a output buffer until the number of cells potentially waiting in that output buffer has dropped below a predetermined threshold. Buffer usage is balanced across the switch by changing the order in which buffers receive misrouted input signals. At the onset of congestion, signals are discarded when necessary at predetermined priority-dependent buffer signal occupancy thresholds. Multicasting can be handled by initially treating a multicast signal as a misrouted signal. The multicast signal is first routed to a merged buffer which did not receive a correctly routed signal, then it is rerouted simultaneously to all of the merged buffers corresponding to its output port destinations, so that all signals can be then sent to the appropriate output ports during a subsequent time period.