High-speed, low power, medium resolution analog-to-digital converter and

Abstract

A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digital-to-analog converter are coupled to supply corrected reference voltages to each track/hold circuit. Outputs of the comparators are supplied to a decoder which produces the digital output representative of the input voltage. The converter is calibrated before it is used for conversion by sensing the input offset voltages of each of the comparators and by altering the reference voltage for each comparator to produce a calibrated reference voltage for each comparator. A digital representation of the calibrated reference voltage for each comparator is stored in a look-up table for retrieval as needed to supply to a particular track/hold circuit a corresponding calibrated analog reference voltage for a particular comparator. Digital representations in the look-up table may indicate switch settings required to provide corrected reference voltages, or may indicate the required corrected reference voltage that is supplied by digital to analog converter which converts the digital representation into an analog corrected reference voltage that is held by the track/hold circuit. In this manner, each track/hold circuit is loaded with its respective calibrated reference voltage. An input signal applied to each comparator triggers such comparators upon parity between the corrected reference voltage and input voltage, and all comparator outputs are supplied to a decoder which produces a digital representation of the input signal. Occasionally, the entries in the look-up table and each track/hold circuit may be refreshed or updated in order to compensate for drift of the calibrated reference voltage.