Address translation device storage last address translation in register

Abstract

The address translation device includes a virtual page number register for storing a last-accessed virtual page number, a physical page number register for storing a physical page number corresponding to the virtual page number stored in the virtual page number and a TLB (translation lookaside buffer) circuit for storing a plurality of relationships between the physical page numbers and the virtual page numbers. First, a comparator compares a new virtual page number with an output of the virtual page number register. If the new virtual page number matches the output of the virtual page number register, the output of the physical page number register is output through a multiplexer as a physical page number. If the new and stored page numbers do not match, on the other hand, a mismatch signal output by the comparator activates the TLB circuit so that the output of the TLB circuit is outputted through a multiplexer as the physical page number. Different configurations of the TLB circuit are used in such a way that the processing speed can be secured without reducing the hit ratio of the address translation. Further, the access to the TLB circuit is minimized to reduce the power consumption.