The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 1999
Filed:
Feb. 14, 1997
Applicant:
Inventors:
Duane G Breid, Lakeville, MN (US);
Roger Roisen, Minnetrista, MN (US);
Ronald D Isliefson, Lakeville, MN (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711118 ; 711-4 ; 711200 ; 395381 ; 395383 ; 365 49 ; 36518901 ; 36518902 ; 36518905 ; 36523003 ;
Abstract
A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.