The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 1999
Filed:
Mar. 28, 1997
Applicant:
Inventor:
Peter Poechmueller, Burlington, VT (US);
Assignee:
Siemens Aktiengesellschaft, Munich, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365200 ; 365222 ; 3652257 ; 36523003 ; 36523008 ; 365233 ; 365240 ;
Abstract
Disclosed is a semiconductor memory having a main memory cell array and redundant memory cells, with a plurality of fuses that can be physically separated from their associated fuse latches. Physical separation is possible by incorporating serial transfer circuitry to serially transfer fuse data from the fuses towards the latches. As a result, only a small number of wires are needed to connect the fuses to the fuse latches, allowing for flexible fuse placement within the memory.
Poechmueller, Peter. (1999). Flexible fuse placement in redundant semiconductor memory (U.S. Patent No. 5859801). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5859801
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile