The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 1999
Filed:
Apr. 15, 1997
Seiji Hirade, Hamamatsu, JP;
Yamaha Corporation, Hamamatsu, JP;
Abstract
Regions of n.sup.+ - and p.sup.+ -types of a semiconductor device are interconnected with a laminated wiring having a low wiring resistance. On the surface of a semiconductor substrate (10), an insulating film (20) is formed covering a field insulating film (12). Contact holes for the n.sup.+ - and p.sup.+ -type regions are formed in the insulating film (20) at areas corresponding to the n.sup.+ - and p.sup.+ -type regions. Thereafter, a refractory metal layer (30A) such as Ti for forming an ohmic contact having a thickness of 100 angstroms or less, an impurity diffusion preventing conductive layer (32A) such as TiN layer, and a refractory metal layer or refractory metal silicide layer (34A) such as W or WSi layer, are formed sequentially in this order from the bottom. A laminated structure of these layers (30A, 32A, 34A) is patterned to form a wiring layer (36). The laminate is subjected to rapid thermal annealing for ohmically contacting the laminate to the n.sup.+ and p.sup.+ -type regions.