The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 1999
Filed:
May. 15, 1997
Muh-rong Yang, Taipei, TW;
Gin-Kou Ma, Chutung, TW;
Other;
Abstract
An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an N.times.N first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the N.times.N network are .rho..sup.k groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to �log.sub.2 N/log.sub.2 .rho.!.sup.-1 and .rho. equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/.rho.. To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are .rho..sup.k groups of (N/.rho..sup.k).times.(N/.rho..sup.k) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of .rho..sup.k groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.