Logic synthesis method and system with intermediate circuit files

Abstract

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction. The system includes a logic input device for inputting an old logic, an old circuit generated from the old logic and optimized to satisfy the design constriction, and a new logic partially changing from the old logic file, a logic synthesizing device for generating a first intermediate circuit file from the new logic file, a discriminating device for discriminating a common sub-circuit of the old circuit having an equivalent logic function and an uncommon sub-circuit of the first intermediate circuit having an inconsistent logic function, from the old circuit and the first intermediate circuit, a circuit updating device for generating a second intermediate circuit file by merging the common sub-circuit of the old circuit and the uncommon sub-circuit of the first intermediate circuit, and an optimizing device for optimizing the uncommon sub-circuit of the second intermediate circuit so as to satisfy the design constriction.