The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 1999

Filed:

Jun. 05, 1997
Applicant:
Inventors:

Sumiko Maeda, Yokohama, JP;

Hisataka Fukase, Yokohama, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ; 36446803 ; 36446809 ; 36447424 ; 395 21 ; 706919 ; 706922 ; 326 41 ;
Abstract

In a method for managing design data regarding an electronic circuit in order to design and analyze the electronic circuit, the design data is arranged according to a hierarchical-layer module structure. The design data in each of hierarchical layers of the hierarchical-layer module structure is divided into objects. The objects together for each of the hierarchical layers are connected together and the objects are connected together over the hierarchical layers. The design data including design data having different items and design data having different data lengths is integrally managed.


Find Patent Forward Citations

Maeda, Sumiko. (1999). Method for making electronic circuit design data and cad system using (U.S. Patent No. 5856925). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5856925

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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