The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 1999
Filed:
Jun. 12, 1996
Noel D Scott, Fort Collins, CO (US);
John R Pessetto, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A clamping system is designed to clamp floating point values from a geometry accelerator in a computer graphics system. The clamping system includes a register configured to receive the floating point value from a connection from the geometry accelerator in the graphics system. Logic associated with the register is configured to determine when the value is less than or equal to a first threshold value (preferably, 0), greater than or equal to a second threshold value (preferably, 1), and between the first and second threshold values. An output mechanism is controlled by the logic. In the preferred embodiment, the output mechanism is a multiplexer interconnected with a tristate driver. The output mechanism is configured to output onto the connection the first threshold value when the color value is less than or equal to the first threshold value, to output onto the connection the second threshold value when the color value is greater than or equal to the second threshold value, and to output onto the connection the originally received floating point value when the floating point value is between the first and second threshold values. An absolute value logic mechanism is associated with the clamping system. The absolute value logic mechanism is configured to force a sign bit of the value that is output by the output mechanism to exhibit a positive state so that the absolute value of an incoming floating point value can be accomplished.