The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 1999
Filed:
Jun. 17, 1996
Applicant:
Inventor:
Bruce E Petrick, Sunnyvale, CA (US);
Assignee:
Sun Microsystems, Inc., Palo Alto, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 17 ; 326 93 ; 327407 ;
Abstract
A 'slow' signal is not sent across chip to be combined with combinatorial logic, but rather, the logic with which it would be combined is partitioned such that there are two outputs, one if the 'slow' signal would be true and a second if the 'slow' signal would be false. Both of these outputs are then provided to a multiplexer. The original 'slow' signal selects the correct signal, thus saving the interconnect time delay. The concepts also apply to combinations of multiple 'slow' signals.
Quick Actions:
Petrick, Bruce. (1999). Logic speed-up by selecting true/false combinations with the slowest (U.S. Patent No. 5856746). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5856746
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile