The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 1999
Filed:
May. 05, 1997
Albert Bergemont, Palo Alto, CA (US);
Min-hwa Chi, Palo Alto, CA (US);
National Semiconductor Corp., Santa Clara, CA (US);
Abstract
A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM cell access transistor and the EEPROM cell storage cell structure, respectively.