The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 1998
Filed:
Jan. 19, 1996
Applicant:
Inventor:
Anant Agarwal, Framingham, MA (US);
Assignee:
IKOS Systems, Inc., North Waltham, MA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364489 ; 364490 ; 364491 ; 364578 ;
Abstract
A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a 'flat mincut' approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a 'hierarchical mincut' in conjunction with a virtual wire cost constraint.