The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 1998
Filed:
Jun. 24, 1997
Sanjay K Jha, San Diego, CA (US);
Jian Lin, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.