The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 1998
Filed:
Apr. 15, 1997
Hiroshi Toyoshima, Akiruno, JP;
Masashige Harada, Fuchu, JP;
Tomohiro Nagano, Akishima, JP;
Yoji Nishio, Hitachi, JP;
Atsushi Hiraishi, Kodaira, JP;
Kunihiro Komiyaji, Hachioji, JP;
Hideharu Yahata, Chofu, JP;
Kenichi Fukui, Kodaira, JP;
Hirofumi Zushi, Fussa, JP;
Takahiro Sonoda, Fuchu, JP;
Haruko Kawachino, Urawa, JP;
Sadayuki Morita, Higashi-Yamato, JP;
Hitachi, Ltd, Tokyo, JP;
Hitachi ULSI Engineering Corp., Tokyo, JP;
Abstract
A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.