The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 1998

Filed:

Jan. 13, 1997
Applicant:
Inventors:

Sadayuki Matsumoto, Tokyo, JP;

Takashi Hashimoto, Tokyo, JP;

Takahiro Urakabe, Tokyo, JP;

Shigeki Harada, Tokyo, JP;

Masao Karino, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ;
U.S. Cl.
CPC ...
3151691 ; 3151694 ; 345204 ; 345215 ;
Abstract

A method of driving a plasma display panel for generating picture or image with high quality while suppressing luminance to a low level in the display in black. One field for image display is composed of at least two different types of subfields first and second subfields. In the first subfield (subfield A), a reset period is provided in which after a priming pulse (Pp) having a voltage value and a pulse width has been applied between X- and Y-row electrodes for causing discharge to occur in all of pixels, then the voltage applied between both the electrodes is set to zero for erasing wall charge after the discharge of all of the pixels, while in the second subfield (subfield B), a reset period is provided in which an erasing pulse (Ep) having a voltage value and a pulse width for causing only the pixels discharged in the preceding subfield to be discharged has been applied for allowing only the pixels discharged in the preceding subfield to be discharged, the wall charge is erased by setting to zero the voltage applied between the X- and Y-row electrodes.


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