The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 1998

Filed:

Sep. 20, 1996
Applicant:
Inventor:

Kamran Manteghi, Manteca, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ; H05K / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257735 ; 257737 ; 257738 ; 257780 ; 257690 ;
Abstract

A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.


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