The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 1998

Filed:

Nov. 19, 1996
Applicant:
Inventors:

Richard Bealkowski, Austin, TX (US);

Doyle Stanfill Cronk, Austin, TX (US);

Benjamin Russell Grimes, Austin, TX (US);

Michael Robert Turner, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39580001 ; 395412 ; 395413 ; 395415 ; 395416 ; 395417 ; 395418 ; 395419 ; 395410 ;
Abstract

A method for managing a memory address space in a memory system, the memory system having multiple block address translation entries, each entry defining a portion of the memory address space, including the steps of determining that a received virtual address references a portion of the memory address space not defined by any of the block address translation entries, reallocating at least one of the block address translation entries to define a portion of the memory address space including the received virtual address, and providing a physical address matching the virtual address by using the reallocated block address translation entries. In addition, an apparatus for managing a memory address space in a memory system, the memory system having multiple block address translation entries, each entry defining a portion of the memory address space, including apparatus for determining that a received virtual address references a portion of the memory address space not defined by any of the block address translation entries, apparatus for reallocating at least one of the block address translation entries to define a portion of the memory address space including the received virtual address, and apparatus for providing a physical address matching the virtual address by using the reallocated block address translation entries.


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