The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1998
Filed:
Dec. 12, 1995
Noriko Shinomiya, Osaka, JP;
Masahiko Toyonaga, Hyogo, JP;
Masahiro Fukui, Osaka, JP;
Toshiro Akino, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area. By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.