The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1998
Filed:
May. 29, 1997
Joze Bevk, Summit, NJ (US);
Matthias Werner Fuertsch, Gomaringen, DE;
George E Georgiou, Gillette, NJ (US);
Steven James Hillenius, Summit, NJ (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
The invention is directed to a process for forming p.sup.+ and n.sup.+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected to a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is performed after the n-type dopant is implanted into the structure. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n.sup.+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.