The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 1998

Filed:

Jun. 05, 1995
Applicant:
Inventor:

Uwe Kranich, Munich, DE;

Assignee:

Advanced Micro Devices, Inc., Sunyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395471 ; 395449 ; 395461 ;
Abstract

A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level. This process continues until the memory access does not hit a particular cache level or until the lowest cache level is reached.


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