The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1998
Filed:
Dec. 26, 1995
Richard L Kapusta, San Jose, CA (US);
Christopher W Jones, Pleasanton, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
The macrocell is configured to allow a single register to be employed either as a register for storing internal macrocell product terms (or logical combinatorial thereof) or as an input register for directly storing signals received from an input/output pin. One embodiment of the macrocell, described herein, includes the register and the input/output pin, along with three two-to-one multiplexers and an output enable logic unit. Feedback lines are also provided. The components are interconnected and appropriate multiplexer and output enable selection signals are provided to allow the macrocell to input and output a variety of combinations of signals including combinatorial and registered logic signals, buried combinatorial and buried registered logic signals, and input and output signals. In one exemplary mode, the macrocell is controlled to store an input signal in the register with the output signal of this register routed to one of the feedback lines while also providing a buried combinatorial feedback path from the macrocell logic line input onto another of the feedback lines. Contents of the register may be output from the macrocell to the input/output pin or fedback along one of the feedback lines to other components of a device containing the macrocell such as a programmable interconnect matrix of a complex programmable logic device. Method and apparatus embodiments of the invention are provided.