Non-volatile programmable cmos logic cell and method of operating same

Abstract

A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The first transistor is coupled in series between a first voltage supply terminal and an output terminal, while the second transistor is coupled in series between a second voltage supply terminal and the output terminal. The first and second transistors share a common floating gate and a common control gate, which extends over the common floating gate. The floating gate has substantially the same layout as the control gate. When the floating gate is programmed to store charge of a first polarity, the programmable logic cell enters a non-volatile first state and provides an output signal having a first logic state. When the floating gate is programmed to store charge of a second polarity, the programmable logic cell enters a non-volatile second state and provides an output signal having a second logic state. When the floating gate is programmed to store a neutral charge, the programmable logic cell enters a third state in which the programmable logic cell provides an output signal representative of a predetermined logic function in response to one or more input signals. This logic function can be, for example, an inverter function, a logical NAND function, or a logical NOR function. The output terminal of the programmable logic cell can be coupled to a pass transistor of a programmable interconnect structure or to a configurable logic block of a field programmable gate array.