The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1998
Filed:
Aug. 22, 1996
Applicant:
Inventor:
Masaru Uya, Osaka, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36478401 ;
Abstract
An improved full subtracter is disclosed which receives a minuend signal A having a weight of +1, a subtrahend signal B having a weight of -1 and a borrow input signal Xi having a weight of -1 and provides a difference output: signal D having a weight of +1 and a borrow output signal Xo having a weight of -2. The full subtracter is composed of CMOS transistors such that both the signal D delay time and the signal Xo delay time are decreased by reducing the number of logic gate stages.
Quick Actions:
Uya, Masaru. (1998). Full subtracter (U.S. Patent No. 5847983). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5847983
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