The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1998
Filed:
Oct. 10, 1996
Donald R Cutler, Portland, OR (US);
Robert M Pailthorp, Portland, OR (US);
Mark A Unrath, Aloha, OR (US);
Thomas W Richardson, Beaverton, OR (US);
Alan J Cable, Beaverton, OR (US);
Electro Scientific Industries, Inc., Portland, OR (US);
Abstract
A multi-rate, multi-head positioner (150) receives and processes unpanelized positioning commands to actuate slow stages (56, 58) and multiple fast stages (154) that are mounted on one of the slow stages to simultaneously position multiple tools (156) relative to target locations (162) on multiple associated workpieces (152). Each of the fast stages is coupled to a fast stage signal processor (172) that provides corrected position data to each fast stage positioner to compensate for fast stage nonlinearities and workpiece placement, offset, rotation, and dimensional variations among the multiple workpieces. When cutting blind via holes in etched circuit boards (ECBs), improved throughput and process yield are achieved by making half of the tools ultraviolet ('UV') lasers, which readily cut conductor and dielectric layers, and making the other half of the tools are infrared ('IR') lasers, which readily cut only dielectric layers. The UV lasers are controlled to cut an upper conductor layer and a portion of an underlying dielectric layer, and the IR lasers are controlled to cut the remaining dielectric layer without cutting through or damaging a second underlying conductor layer. The throughput is increased by cutting conductor layers in unprocessed ECBs while concurrently cutting dielectric layers in ECBs that have already had their conductor layer cut. The process yield is increased by performing a workpiece calibration prior to each cutting step to account for any ECB placement, offset, rotation, and dimensional variations.