The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1998
Filed:
Nov. 27, 1996
Kil Ho Lee, Kyoungkido, KR;
Byung Jin Cho, Kyoungkido, KR;
Abstract
Disclosed is a method for the shallow junction having a low sheet resistance and an improved electric characteristics, using the medium temperature CVD oxide layer deposited on the source/drain regions into which impurity ions are implanted. The medium temperature CVD oxide layer, which has a compressive stress of 1.53.times.10.sup.9 dyne/cm.sup.2, causes the surface of the silicon substrate to be subject to tensile stress. By forming the medium temperature CVD oxide layer on the silicon substrate at a temperature of approximately 760.degree.-820.degree. C., the defects in the inside of the substrate move to the surface of the silicon substrate. As a result, the concentration of the defects in the inside of the silicon substrate decreases so that the small size extended defects are on the surface of the silicon substrate. These extended defects can be naturally removed from the surface of the silicon substrate by performing a follow-up process such as a metalization or an additional thermal treatment process.