The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1998
Filed:
Apr. 24, 1997
Tamotsu Ichikawa, Kanagawa, JP;
Masao Komatsu, Kanagawa, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
A hierarchical processing system includes processors connected in a hierarchical formation having first, second and third hierarchical levels, for down loading information to the processors in parallel. The system comprises a memory unit provided at the first hierarchical level, for storing information to be down loaded to the processors located at the second and third hierarchical levels and for receiving configuration data about the processors located at the second and third hierarchical levels therefrom, a receiving unit provided at the second hierarchical level, for receiving the information to be down loaded to the processors located at the second and third hierarchical levels from the memory unit and for sending the configuration data about processors located at the second and third hierarchical levels to the memory unit. Another receiving unit is provided at the third hierarchical level, for receiving the information to be down loaded to the processors located at the third hierarchical level from the memory unit via the first receiving unit and for sending the configuration data about the processors located at the third hierarchical level to the first receiving unit. Thus, the memory unit can store the information to be down loaded to the processors and send the information to the processors on the basis of the configuration data.