Method and nonvolatile semiconductor memory for repairing over-erased

Abstract

In a nonvolatile floating gate memory cell array, memory cells can become over-erased wherein their threshold voltage becomes near zero volts or even slightly negative. To correct over-erased cells and raise their threshold voltages to a normal level, a nonvolatile memory includes a control circuit for applying a programming voltage (approximately 5V) to the bit lines of the memory cell array and a lower voltage (approximately 2V) to the word lines of the memory cell array. The lower voltage is selected to be less than the threshold voltage (e.g., 3V) for a normal cell such that normal cells are not affected. However, the cells in an over-erased state will become active by the lower threshold voltage and begin conducting. A channel current flows to the over-erased memory cells and channel hot electrons induced by this channel flow into the floating gate of the memory cell raises the threshold voltage (VTM) of the memory cell to a normal level.