The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1998
Filed:
Jan. 10, 1997
Tim Phoenix, Gilbert, AZ (US);
Microchip Technology, Incorporated, Chandler, AZ (US);
Abstract
A high voltage data latch with complementary outputs that are each set to one of two voltage levels (V.sub.pp and V.sub.b). The high voltage data latch is designed using CMOS technology wherein no PMOS transistors have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used. The high voltage data latch has two modes of operation. In a low voltage mode (V.sub.pp =V.sub.DD and V.sub.b =Ground) the outputs switch with respect to the inputs. In a high voltage mode (V.sub.pp >V.sub.b >V.sub.dd) the outputs will be latched to the state they were in when the voltage rails changed states from the low voltage mode to the high voltage mode.