The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 1998

Filed:

Jul. 19, 1996
Applicant:
Inventors:

Hung T Nguyen, San Jose, CA (US);

Chit Ah Mak, Fremont, CA (US);

Steve W Liu, Homebush, AU;

Assignee:

Quality Semiconductor, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 58 ; 326 81 ; 326 86 ; 36518505 ; 36518909 ;
Abstract

An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.


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