Self-aligned pocl.sub.3 process flow for submicron microelectronics

Abstract

In a method of introducing phosphorous into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the lightly doped drain (LDD) implant step, with the exception, that, in this case, the gate polysilicon remains undoped. In accordance with the invention, dopant is then implanted into the source/drain regions such that the undoped gate polysilicon is amorphized, thereby eliminating the polysilicon grain boundaries. A CVD oxide layer is then formed and a CMP step is performed to expose the amorphized gate polysilicon region. A phosphorous oxychloride (POCl.sub.3) layer is then formed over the amorphized gate polysilicon and thermally annealed to drive phosphorous from the POCl.sub.3 layer into the polysilicon. The POCl.sub.3 layer is then removed.