On-chip programming verification system for plds

Abstract

The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells. To verify PLD programming, the invention applies a signature analyzer coupled between the TDI and TDO pins. A single input linear feedback shift register (SISR) or multiple LFSR (MISR) can be used to implement a signature analyzer in accordance with the invention. SISR or MISR uses a characteristic polynomial to generate a near-unique signature checksum for an input sequence. The accumulated signature checksum is then provided serially through the TDO pin for inspection.