Semiconductor memory device having synchronous write driver circuit

Abstract

A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.