The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 1998
Filed:
Feb. 13, 1996
Athanasius W Spyrou, San Jose, CA (US);
Michael Grossman, Mt. View, CA (US);
Michael Misheloff, Dublin, CA (US);
Thomas Schaefer, Cupertino, CA (US);
Marie C Salet, Fremont, CA (US);
Clementina Bures, Santa Clara, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.