The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 1998
Filed:
Apr. 11, 1997
Norihide Kinugasa, Kyoto, JP;
Mitsuhiko Otani, Hyogo, JP;
Katsumi Hironaka, Osaka, JP;
Shinichi Ogita, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.L are not changed by the voltage V.sub.IN of the input analog signal. Consequently, a settling time can be shortened more than in the prior art.