Digital pll using phase and frequency error calculating circuits

Abstract

An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.