The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 1998

Filed:

May. 31, 1996
Applicant:
Inventors:

Howard Charles Nicholls, Cardiff, GB;

Michael John Norrington, Clacton on Sea, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257383 ; 257641 ; 257752 ; 257763 ;
Abstract

A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together. The invention also provides a method of fabricating a semiconductor device incorporating a refractory metal contact, the method comprising the steps of: a) providing a semiconductor substrate having an oxide layer thereon and a doped polysilicon region disposed on the oxide layer; (b) depositing a dielectric layer over the doped polysilicon region and over the silicon substrate; (c) forming a contact hole in the dielectric layer which exposes a portion of the doped polysilicon region and a laterally adjacent portion of the silicon substrate; and (d) selectively depositing a contact into the contact hole thereby electrically to connect together the doped polysilicon region and the silicon substrate.


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