The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 1998
Filed:
Mar. 31, 1997
Applicant:
Inventors:
Robert M Salter, III, Saratoga, CA (US);
Kyung Joon Han, Cupertino, CA (US);
Jack Zezhong Peng, San Jose, CA (US);
Victor Levchenko, San Francisco, CA (US);
Robert V Broze, Santa Cruz, CA (US);
Assignee:
GateField Corporation, Fremont, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257321 ; 257326 ; 36518521 ;
Abstract
Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.