The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 1998
Filed:
Dec. 05, 1995
Masayuki Ikeda, Kanagawa, JP;
Fujitsu Limited, Kawasaki-ku, JP;
Abstract
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.