Digital data separator for separating data signals from clock signals in

Abstract

A digital data separator for separating data signals from clock signals contained in an encoded data stream in alternating data/clock slots without requiring a phase-locked loop. The digital data separator comprises: (a) a system clock source for generating system clock pulses; (b) an up-counter coupled to the system clock source for incrementing a system clock count, the up-counter is structured such that the system clock count is incremented by the system clock pulses and is reset to zero upon receiving a reset signal; (c) a state generator containing an edge detector for detecting an edge transition in an input signal within a predetermined range of system clock counts, and a combination logic for generating a data control signal, a reference clock control signal, and the reset signal when such edge transition in the input signal is detected within the predetermined range of system clock counts or when the system clock counts reaches a predetermined value; and (d) a window and data generator for generating regenerated clock and data signals in response to the data control signal and the reference clock control signal received from the state generator.