Semiconductor memory

Abstract

In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal. A pair of address comparing circuits to which supplied is an internal column address to be successively updated according to the data burst length, alternately supply a redundancy judgement signal after alternately comparing the same defective column address previously programmed therein, with an internal column address according to the complementary clock signals supplied from the frequency dividing circuit. The output circuit supplies a redundancy judgement signal when either of the judgement signals is obtained. Thus, there is made an accurate column redundancy judgement at the time when the external clock signal is high in frequency.