Interconnect scheme for integrated circuits

Abstract

A novel interconnect layout method and metallization scheme is provided that simplifies the process of fabricating multilayer interconnects. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. No specific process module is needed for contact layers. The use of patterned metal layers formed from the same process modules makes both design and construction of multilayer interconnects simpler. Accordingly, the manufacturing process is simplified, thus resulting in lower cost. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other. In this manner, vertical low ohmic bussing is made possible.