Digital signal processor and associated method for conditional data

Abstract

A digital signal processor that includes an execution unit, a condition code register, a program memory, a program control unit, and an instruction decoder. The program memory stores a sequence of instruction words and includes an instruction word that has at least one field that identifies a data processing operation to be performed by the execution unit. The instruction word also includes a condition code field that identifies a predefined condition and also identifies whether said condition code register should be updated when the data processing operation is performed by the execution unit. The program control unit outputs an instruction address to the program memory so as to select the instruction word in the program memory. The instruction decoder decodes the selected instruction word. It includes decoder circuitry for decoding the at least one field to generate control signals for controlling the execution unit to perform the specific data processing operation. The execution unit includes means for generating a current condition code flag if a corresponding predefined condition occurs when the execution unit performs the current data processing operation in response to the control signals. The instruction decoder further includes condition code decoder circuitry for decoding the condition code field to generate a control signal for enabling and disabling the condition code register to store the current condition code flag in accordance with the condition code field's value.