The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 1998

Filed:

Oct. 09, 1997
Applicant:
Inventor:

Yuejian Wu, Kanata, CA;

Assignee:

Northern Telecom Limited, Montreal, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 224 ; 371 2233 ;
Abstract

An analytical fault diagnostic methodology for use in complex VLSI chips. The method assumes a scan design environment and is capable of locating errors to the scan flops that capture the errors during test, independently of the number of errors that the circuit-under-test produces. The methodology is also capable of identifying the test vector or vectors under which the errors are generated. The apparatus which is designed to implement the method is also described. As the apparatus requires little hardware, the method is practical for chip level applications.


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Wu, Yuejian. (1998). Methods and apparatus for fault diagnosis in self-testable systems (U.S. Patent No. 5831992). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5831992

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