The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 1998
Filed:
Sep. 06, 1996
Applicant:
Inventors:
Yasuhiko Nitta, Hyogo, JP;
Masaki Tsukude, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523003 ; 365233 ; 36523002 ;
Abstract
One memory array is divided into a plurality of banks sharing a row of memory cells. Global IO buses are disposed for memory column blocks forming the plurality of banks included in one memory array. The global IO buses are selectively and electrically connected to the same data input/output terminal.
Nitta, Yasuhiko. (1998). Synchronous semiconductor memory device having a plurality of banks (U.S. Patent No. 5831924). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5831924
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile