Local power failure detection and clock disabling circuit

Abstract

A local power failure detection and clock disabling circuit operates within a node coupled to a bus structure. The node includes multiple ports and physical connections for supporting multiple applications. Each physical connection serves as a bus transceiver for receiving and transmitting communications over the bus structure. The node includes a local power supply and a clock signal which is provided to each of the physical connections within the node. A detection circuit is coupled to the local power supply for detecting whether or not a sufficient level of power is being supplied from the local power supply. The clock signal is always provided to a master physical connection within the node, which is responsible for repeating communications across the bus structure. The master physical connection draws power from the backup power supply source when the local power supply is not supplying a sufficient level of power. When the detection circuit has detected that the local power supply is not supplying a sufficient level of power, the clock signal is disabled to all of the physical connections within the node, except the master physical connection, in order to minimize power consumption of the node. The local applications coupled to the node are also disabled when a sufficient level of power is not supplied from the local power supply. When the detection circuit detects that the local power supply is again supplying power at a sufficient level, the clock signal is reenabled to all of the physical connections within the node and the local applications are also reenabled.